A programmable logic device, such as a field programmable gate array (FPGA), may be used in a wide variety of applications. For example, a programmable logic device (PLD) offers the advantage of being reprogrammable in the field (e.g., while on the circuit board in its operational environment) to provide the desired functionality.
A typical PLD includes a number of programmable logic blocks (e.g., also referred to in the art as configurable logic blocks, logic array blocks, or programmable function blocks). The programmable logic block architecture may be generally categorized as having a slice-based structure or a block-based structure. A slice may provide, for example, a 2-bit slice structure (e.g., two 4-bit lookup tables (LUTs) plus two registers), with the programmable logic block formed by two slices. A block may provide, for example, eight or more 4-bit LUTs and associated registers, with the programmable logic block formed by the block structure.
A drawback of the conventional PLD is that the programmable logic block architecture is often not optimized for the desired application. For example, the programmable logic blocks are generally homogeneous with each having the same one or two slices or each having the same block structure. Consequently, the programmable logic block architecture is not optimized for the desired application and results in unused resources, larger than necessary die size, and inefficient scaling for providing a larger number of LUTs within the PLD. Furthermore, these conventional approaches often result in inefficient control architectures as the programmable logic device increases in size and/or logic block granularity. As a result, there is a need for improved programmable logic block architectures for PLDs.